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INTEGRATED CIRCUITS
74ALVCH16373 2.5V/3.3V 16-bit D-type transparent latch (3-State)
Product specification Supersedes data of 1998 Jun 29 IC24 Data Handbook 1999 Sep 20
Philips Semiconductors
Philips Semiconductors
Product specification
16-bit D-type transparent latch (3-State)
74ALVCH16373
FEATURES
* Wide supply voltage range of 1.2V to 3.6V * Complies with JEDEC standard no. 8-1A * CMOS low power consumption * MULTIBYTETM flow-through standard pin-out architecture * Low inductance multiple VCC and ground pins for minimum noise
and ground bounce
PIN CONFIGURATION
1OE 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 1 2 3 4 5 6 7 8 9 48 1LE 47 1D0 46 1D1 45 GND 44 1D2 43 1D3 42 VCC 41 1D4 40 1D5 39 GND 38 1D6 37 1D7 36 2D0 35 2D1 34 GND 33 2D2 32 2D3 31 VCC 30 2D4 29 2D5 28 GND 27 2D6 26 2D7 25 2LE
* Direct interface with TTL levels * All data inputs have bus hold * Output drive capability 50 transmission lines @ 85C * Current drive 24 mA at 3.0 V
DESCRIPTION
The 74ALVCH16373 is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs. One latch enable (LE) input and one output enable (OE) are provided per 8-bit section. The 74ALVCH16373 consists of 2 sections of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches.
GND 10 1Q6 11 1Q7 12 2Q0 13 2Q1 14 GND 15 2Q2 16 2Q3 17 VCC 18 2Q4 19 2Q5 20 GND 21 2Q6 22 2Q7 23 2OE 24
SW00066
QUICK REFERENCE DATA
GND = 0V; Tamb = 25C; tr = tf 2.5ns SYMBOL PARAMETER Propagation delay g y Dn to Qn tPHL/tPLH Propagation delay g y LE to Qn Input capacitance Power dissipation capacitance per latch VI = GND to VCC1 Outputs enabled Outputs disabled CONDITIONS VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF TYPICAL 2.1 2.1 2.2 2.2 5.0 16 10 pF pF ns UNIT
CI CPD
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL x VCC2 x fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES 48-Pin Plastic SSOP Type III 48-Pin Plastic TSSOP Type II TEMPERATURE RANGE -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74ALVCH16373 DL 74ALVCH16373 DGG NORTH AMERICA ACH16373 DL ACH16373 DGG DWG NUMBER SOT370-1 SOT362-1
1999 Sep 20
2
853-2086 22418
Philips Semiconductors
Product specification
16-bit D-type transparent latch (3-State)
74ALVCH16373
PIN DESCRIPTION
PIN NUMBER 1 2, 3, 5, 6, 8, 9, 11, 12 4, 10, 15, 21, 28, 34, 39, 45 7, 18, 31, 42 13, 14, 16, 17, 19, 20, 22, 23 24 25 36, 35, 33, 32, 30, 29, 27, 26 47, 46, 44, 43, 41, 40, 38, 37 48 SYMBOL 1OE 1Q0 to 1Q7 GND VCC 2Q0 to 2Q7 2OE 2LE 2D0 to 2D7 1D0 to 1D7 1LE NAME AND FUNCTION Output enable input (active LOW)
LOGIC SYMBOL
1 24
1OE
2OE 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23
Data inputs/outputs Ground (0V) Positive supply voltage Data inputs/outputs Output enable input (active LOW) Latch enable input (active HIGH) Data inputs Data inputs Latch enable input (active HIGH)
47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 1LE 2LE
48
25
SW00067
LOGIC DIAGRAM
1D0 D Q 1Q0 2D0 D Q 2Q0
LATCH 1 LE LE
LATCH 9 LE LE
1LE 1OE
2LE 2OE
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
SW00068
FUNCTION TABLE (per section of eight bits)
INPUTS OPERATING MODES nOE Enable and read register (transparent mode) Latch and read register (hold mode) Latch register and disable outputs H h L l X Z L L L L H H nLE H H L L L L nDn L H l h l h INTERNAL LATCHES L H L H L H OUTPUTS nQn L H L H Z Z
= HIGH voltage level = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition = LOW voltage level = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition = don't care = high impedance OFF-state
1999 Sep 20
3
Philips Semiconductors
Product specification
16-bit D-type transparent latch (3-State)
74ALVCH16373
LOGIC SYMBOL (IEEE/IEC)
1OE 1LE 2OE 2LE 1 48 24 25 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 4D 2 1EN C3 2EN C4 3D 1 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
BUS HOLD CIRCUIT
VCC
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7
Data Input
To internal circuit
SW00044
SW00524
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL PARAMETER DC supply voltage 2.5V range (for max. speed performance @ 30 pF output load) VCC DC supply voltage 3.3V range (for max. speed performance @ 50 pF output load) For data input pins VI VO Tamb tr, tf DC Input voltage range For control pins DC output voltage range Operating free-air temperature range Input rise and fall times VCC = 2.3 to 3.0V VCC = 3.0 to 3.6V 0 0 -40 0 0 CONDITIONS MIN 2.3 3.0 0 MAX 2.7 V 3.6 VCC 5.5 VCC +85 20 10 V C ns/V UNIT
V
1999 Sep 20
4
Philips Semiconductors
Product specification
16-bit D-type transparent latch (3-State)
74ALVCH16373
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC in ut voltage input DC output diode current DC output voltage DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package -plastic medium-shrink (SSOP) -plastic thin-medium-shrink (TSSOP) For temperature range: -40 to +125 C above +55C derate linearly with 11.3 mW/K above +55C derate linearly with 8 mW/K VI t0 For control pins2 For data inputs2 VO uVCC or VO t 0 Note 2 VO = 0 to VCC CONDITIONS RATING -0.5 to +4.6 -50 -0.5 to +4.6 -0.5 to VCC +0.5 "50 -0.5 to VCC +0.5 "50 "100 -65 to +150 850 600 V mA V mA mA C mW UNIT V mA
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VCC = 1.2V VIH HIGH level Input voltage VCC = 1.8V VCC = 2.3 to 2.7V VCC = 2.7 to 3.6V VCC = 1.2V VIL LOW level Input voltage VCC = 1.8V VCC = 2.3 to 2.7V VCC = 2.7 to 3.6V VCC = 1 8 to 3 6V; VI = VIH or VIL; IO = -100A 100A 1.8 3.6V; VCC = 1.8V; VI = VIH or VIL; IO = -6mA VCC = 2.3V; VI = VIH or VIL; IO = -6mA VOH HIGH level output voltage VCC = 2.3V; VI = VIH or VIL; IO = -12mA VCC = 2.3V; VI = VIH or VIL; IO = -18mA VCC = 2.7V; VI = VIH or VIL; IO = -12mA VCC = 3.0V; VI = VIH or VIL; IO = -24mA VCC*0.2 02 VCC*0.4 VCC*0.3 VCC*0.5 VCC*0.6 VCC*0.5 VCC*1.0 0.9 1.2 1.5 VCC VCC*0.10 VCC*0.08 VCC*0.17 VCC*0.26 VCC*0.14 VCC*0.28 V VCC 0.7*VCC 1.7 2.0 0.9 V 1.2 1.5 GND 0.2*VCC 0.7 0.8 V TYP1 MAX UNIT
1999 Sep 20
5
Philips Semiconductors
Product specification
16-bit D-type transparent latch (3-State)
74ALVCH16373
DC ELECTRICAL CHARACTERISTICS (Continued)
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). VCC = 1 8 to 3 6V; VI = VIH or VIL; IO = 100A 1.8 3.6V; VCC = 1.8V; VI = VIH or VIL; IO = 6mA VCC = 2.3V; VI = VIH or VIL; IO = 6mA VOL LOW level output voltage VCC = 2.3V; VI = VIH or VIL; IO = 12mA VCC = 2.3V; VI = VIH or VIL; IO = 12mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VCC = 3.0V; VI = VIH or VIL; IO = 24mA Input leakage current per control pin II Input leakage current per data g pin Input current for common I/O pins 3-State output OFF-state current Quiescent supply current Additional quiescent supply current given per control pin Additional quiescent supply current given per data I/O pin Bus hold LOW sustaining g current Bus hold HIGH sustaining g current Bus hold LOW overdrive current Bus hold HIGH overdrive current VCC = 1.8 to 3.6V; VI = 5.5V or GND VCC = 1.8 to 3.6V; VI = VCC or GND VCC = 1.8 to 2.7V; VI = VCC or GND VCC = 3.6V; VI = VCC or GND VCC = 2.7 to 3.6V; VI = VIH or VIL; VO = VCC or GND VCC = 1.8 to 2.7V; VI = VCC or GND; IO = 0 VCC = 2.7 to 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC - 0.6V; IO = 0 VCC = 2.7V to 3.6V; VI = VCC - 0.6V; IO = 0 VCC = 2.3V; VI = 0.7V VCC = 3.0V; VI = 0.8V VCC = 2.3V; VI = 1.7V VCC = 3.0V; VI = 2.0V VCC = 2.7V VCC = 3.6V VCC = 2.7V VCC = 3.6V 45 75 -45 -75 300 450 -300 -450 -175 GND 0.09 0.07 0.15 0.23 0.14 0.27 0.1 01 0.1 0.1 0.1 0.1 0.2 0.2 150 150 - 150 0 20 0.20 0.30 0.20 0.40 0.60 0.40 0.55 5 A 5 10 15 10 40 40 750 A 750 A A A A V
IIHZ/IILZ IOZ ICC
ICC
IBHL2
IBHH2
A
IBHLO2 O
A
IBHHO2 O
A
NOTES: 1. All typical values are at Tamb = 25C. 2. Valid for data inputs of bus hold parts.
1999 Sep 20
6
Philips Semiconductors
Product specification
16-bit D-type transparent latch (3-State)
74ALVCH16373
AC CHARACTERISTICS FOR VCC = 2.3V TO 2.7V RANGE AND VCC < 2.3V
GND = 0V; tr = tf 2.0ns; CL = 30pF LIMITS SYMBOL PARAMETER WAVEFORM VCC = 2.3 to 2.7V MIN tPHL/tPLH tPHL/tPLH tPZH/tPZL Propagation delay nDn to nYn Propagation delay nLE to nYn 3-State output enable time nOE to nYn 3-State output disable time nOE to nYn nLE pulse width HIGH Set-up time nDn to nLE Hold time nDn to nLE 1, 5 2, 5 1.0 1.0 TYP1, 2 2.1 2.2 MAX 3.9 3.9 MIN 1.5 1.5 VCC = 1.8V TYP1 3.2 3.4 MAX 5.7 5.9 VCC = 1.2V TYP 8.8 7.4 ns ns UNIT
4, 5
1.0
2.6
5.2
1.5
4.0
7.3
8.9
ns
tPHZ/tPLZ tW tSU th
4, 5 2 3 3
1.0 3.0 1.0 1.5
2.2 1.0 -0.1 0.2
4.1 - - -
1.5 3.5 1.0 1.2
3.2 1.0 -0.1 0.1
5.6 - - -
8.9 - - -
ns ns ns ns
NOTES: 1. All typical values are measured at Tamb = 25C. 2. Typical value is measured at VCC = 2.5V.
AC CHARACTERISTICS FOR VCC = 3.0V TO 3.6V RANGE AND VCC = 2.7V
GND = 0V; tr = tf 2.5ns; CL = 50pF LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3V 0.3V MIN tPHL/tPLH tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW tSU th Propagation delay nDn to nYn Propagation delay nLE to nYn 3-State output enable time nOE to nYn 3-State output disable time nOE to nYn nLE pulse width HIGH Set-up time nDn to nLE Hold time nDn to nLE 1, 5 2, 5 4, 5 4, 5 2 3 3 1.0 1.0 1.0 1.0 2.5 1.0 1.2 TYP1, 2 2.1 2.2 2.3 2.8 1.0 0.0 0.2 MAX 3.3 3.2 4.2 4.1 - - - MIN 1.0 1.0 1.0 1.0 3.0 1.0 1.5 VCC = 2.7V TYP1 2.3 2.2 2.9 3.1 1.0 -0.1 0.4 MAX 3.7 3.5 4.9 4.7 - - - ns ns ns ns ns ns ns UNIT
NOTES: 1. All typical values are measured at Tamb = 25C. 2. Typical value is measured at VCC = 3.3V.
1999 Sep 20
7
Philips Semiconductors
Product specification
16-bit D-type transparent latch (3-State)
74ALVCH16373
AC WAVEFORMS FOR VCC = 2.3V TO 2.7V AND VCC < 2.3V RANGE
VM = 0.5 VCC VX = VOL + 0.15V VY = VOH -0.15V VOL and VOH are the typical output voltage drop that occur with the output load. V =V CC I
VI OE INPUT GND VM VM
tPLZ VCC OUTPUT LOW-to-OFF OFF-to-LOW VOL tPHZ VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled VY
tPZL
AC WAVEFORMS FOR VCC = 3.0V TO 3.6V AND VCC = 2.7V RANGE
VM = 1.5 V VX = VOL + 0.3V VY = VOH -0.3V VOL and VOH are the typical output voltage drop that occur with the output load. V = 2.7V I
VI Dn INPUT GND tPHL VOH Qn OUTPUT VOL VM tPLH VM VM
VM VX
tPZH
VM
outputs enabled
SW00072
Waveform 4. 3-State enable and disable times
TEST CIRCUIT
VCC S1 2 * VCC Open GND
SW00070
Waveform 1. Input (Dn) to output (Qn) propagation delays
PULSE GENERATOR
VI D.U.T. RT
VO
RL = 500
CL
RL = 500
VI LE INPUT GND tw tPHL VOH Qn OUTPUT VOL VM VM tPLH VM VM VM
Test Circuit for switching times DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators.
SWITCH POSITION
SW00071
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 < VCC
GND
VCC < 2.7V 2.7-3.6V
VI VCC 2.7V
Waveform 2. Latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays
Dn INPUT
GND
LE INPUT
GND NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
Waveform 3. Data set-up and hold times for the Dn input to the LE input
1999 Sep 20
EEEEEEEEEE EEE E EEE E EEEEEEEEEE EEE EEEEEEEE EEE
VI VM th th tSU tSU VI VM
SV00906
Waveform 5. Load circuitry for switching times
SW00073
8
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit D-type transparent latch (3-State)
74ALVCH16373
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
1999 Sep 20
9
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit D-type transparent latch (3-State)
74ALVCH16373
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm
SOT362-1
1999 Sep 20
10
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit D-type transparent latch (3-State)
74ALVCH16373
NOTES
1999 Sep 20
11
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit D-type transparent latch (3-State)
74ALVCH16373
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 10-99 Document order number: 9397-750-06515
Philips Semiconductors
1999 Sep 20 12

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